1. Field
The present invention relates to a digital-to-analog converter (DAC). More specifically, the present invention relates to a clocked DAC, where a clock prevents the DAC from emitting an output until the DAC inputs have fully switched.
2. Related Prior Art
DACs typically come in two forms, return to zero (RTZ) DACs, where signals return to zero also in absence of a data transition, and non return to zero (NRTZ) DACs, where signals do not return to zero, except during a data transition. DACs typically comprise many transistors, which can be subject to intersymbol interference coming, for example, from thermal hysteresis.
The thermal hysteresis problem will be discussed in more detail with reference to FIG. 1, which shows a prior art DAC comprising a differential pair 10 connected with a current generator 40 and digital inputs IN, INX applied to the differential pair 10. The differential pair 10 comprises transistors Q1 and Q2. The digital inputs IN and INX are applied to the base of Q1 and Q2. The emitters of Q1 and Q2 are connected with the current generator 40. The output of the DAC is an analog current output I1, I2 taken on the collectors 11, 12 of the transistors Q1 and Q2.
The ON condition or OFF condition of a transistor, such as Q1 or Q2, is regulated by its base-emitter voltage VBE(On). The threshold voltage VBE(On) is a function of temperature of the base-emitter junction. The higher the temperature of the junction, the lower the value of VBE(On) required to turn the transistor ON. The lower the temperature of the junction, the higher the value of VBE(On) required to turn the transistor ON.
Reference will now be made also to FIG. 2, which shows logic values of the input signals IN, INX as a function of time and temperature values T(Q1), T(Q2) of the base-emitter junction of transistors Q1, Q2 as a function of time. The digital input INX is the complementary of digital input IN. Digital inputs IN and INX switch aperiodically. Assuming that the starting condition of the IN digital input is a ‘high’ value and the starting condition of the INX digital input is a ‘low’ value, when the IN digital input switches and begins to change from high to low, the temperature T(Q1) of transistor Q1 will begin to change from high to low, as shown in FIG. 2. Similarly, in a complementary manner, the temperature T(Q2) of transistor Q2 will begin to change from low to high, as shown by the dotted line of FIG. 2.
Q1 and Q2 switch for the second time at t2, i.e. when IN, INX switch again. At time t2, T(Q1) has not fully settled to a low temperature value typical of an OFF condition. The value Δ(T1)=|T(Q1)t1−T(Q2)t1| represents the difference between the value of T(Q1) and the value of T(Q2) at time t1. The value Δ(T2)=|T(Q1)t2−T(Q2)t2| represents the difference between the value of T(Q1) and the value of T(Q2) at time t2. It can be noted that |T(Q1)t2−T(Q2)t2|<|T(Q1)t1−T(Q2)t1|. The greater the temperature difference between Q1 and Q2, the longer it will take to switch the output current after the input signal switches. Therefore, when Q1 is switched ON again at the time t2, Q1 will reach an ON condition faster than the previous instance. Similarly, at time t3, when IN, INX switch again, T(Q2) has not fully settled to a low temperature value typical of the OFF condition. The value Δ(T3)=|T(Q1)t3−T(Q2)t3| represents the difference between the value of T(Q1) and the value of T(Q2) at time t3. Therefore, when Q2 is switched ON again at the time t3, Q2 will reach an ON condition faster than at time t2 It follows that there is a variable anticipation or delay in reaching an ON or OFF condition, depending on the value of the temperature differences ΔT1, ΔT2 and ΔT3. This behavior is called thermal hysteresis and could bring to intersymbol interference. Thermal hysteresis is, therefore, unacceptable, because it could be the cause of possible distortion.
A possible solution to the problem of thermal hysteresis in DACs is disclosed in Adams R. and Nguyen, K. Q, “A 113-dB SNR Oversampling DAC with Segmented Noise-Shaped Scrambling,” IEEE Journal of Solid State Circuits, Vol. 33, Issue 12, December 1998, pp. 1871–1878. Adams discusses a NRTZ DAC configuration which relies upon two RTZ DACs with opposite clock phases. However, this configuration relies upon two separate current sources having two different phases, thus requiring double the power dissipation. This kind of dissipation is typical in RTZ DACs where, for a given clock cycle, the DAC is ON half of the time and OFF the other half of the time. An additional problem is due to the different behavior of the two current sources, which causes a slightly different amount of current to go to the output from one clock phase to the next.
Therefore, there is a need for an improved DAC that alleviates the effects of thermal hysteresis and at the same time limits the amount of dissipated power.